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Our Client creates solutions that enable secure connections for a smarter world. Building on its expertise in High Performance Mixed Signal electronics, in the automotive, identification and mobile industries, and in application areas including wireless infrastructure, lighting, healthcare, industrial, consumer tech and computing.
In this exciting role, you are responsible for the delivery of fully verified layout designs (full custom), which meets all technical requirements provided by the designer. The main aspects in the standard analog based design flow are floor planning, transistor level layout and placement of IP, manual routing, full chip verification by DRC, LVS, ERC, package assembly rules and ESD/LU guidelines.
This is all done in a Cadence 5 design environment combined with appropriate tool and sub-micron process knowledge.
· Bachelor degree in Electronic Engineering
· 5+ year experience in Transistor Level IP and I/O Layout
· Skilled on with Cadence, Dracula and Assura Layout tooling
· Owns basic knowledge of Electro Static Discharge and Latch-Up mechanisms
· Experienced in submicron C100–like processes of the Semiconductor industry
· Good communication skills in both Dutch and English
· Target driven, shows initiative and can work independently.
The right candidate will be provided a challenging and varied position in a professional, high-tech environment. An appropriate salary, future prospects and excellent benefits are evident. After a period of secondment and functioning properly, you can be contracted by our client.
Do you feel you are the most suitable person for this position or do you have any further questions?
Send your CV to email@example.com or call 040-4015200 and ask for Ivo Bremer.
firstname.lastname@example.org or call 040-4015200